1. Technical Field
The present application relates generally to computer systems and microprocessors. More particularly, the present application relates to chip multiprocessors.
2. Description of the Background Art
Technology scaling and decreasing power efficiency of uniprocessors has led to the emergence of chip multiprocessors (CMP) as a hardware paradigm. In a CMP, multiple processor cores are integrated on a single chip and are available for general purpose computing.
Components on the die of a CMP (on-chip components) may be shared to improve resource utilization. For example, cores may be shared via hyperthreading, and last level caches and input/output (I/O) interfaces may be shared. In addition, typically off-chip components, such as memory controllers and I/O links, are being integrated onto CMPs.
While the above-mentioned sharing and integration may provide better resource utilization and improved performance, it also results in lower overall reliability. The lower overall reliability is because an error in any one component of the chip may lead to the non-availability of the entire CMP. For example, single processor failure typically results in the loss of availability of all processors on that CMP. Also, failure in a shared component like the cache or memory controller typically affects all the cores sharing that component. The failure in time (FIT) of the individual cores, caches, memory and I/O components may add up to a rather high FIT for the CMP as a whole.